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+--- Thread: PIC18F46K20 (/showthread.php?tid=2279)
PIC18F46K20 - roicho - 2014-07-17
Hello, I have a problem, It doesn't found the boot loader
Initiating write...
Searching for bl . . . . . . . . . . . .
I modified....
ds30loader.asm
--------------------------------------------------------------------------------
; Toggle pin, frequency on pin = PIC frequency / 16
if 0
bcf TRISC, TRISC6
tsfloop bsf LATC, LATC6
bcf LATC, LATC6
bra tsfloop
endif
setting.inc
--------------------------------------------------------------------------------
processor P=18F46K20 ;xxx
;------------------------------------------------------------------------------
; Includes
;------------------------------------------------------------------------------
#include "devices.inc"
;------------------------------------------------------------------------------
; User preferences
;------------------------------------------------------------------------------
radix DEC
#define OSCF 16000000 ;xxx oscillator frequency (including pll)
#define BLINIT 2000 ;xxx hello receive timeout [ms]
#define HELLOTRIES 2 ;xxx number of non hello characters received before branching to the user application
#define BLTIME 2000 ;xxx data receive timeout [ms]
;------------------------------------------------------------------------------
; UART settings
;------------------------------------------------------------------------------
#define USE_UART1 1 ;xxx uncomment to use uart1
;#define USE_UART2 1 ;xxx uncomment to use uart2
#define BAUDRATE 19200 ;xxx baudrate
;#define USE_ABAUD 1 ;xxx uncomment to use auto baud rate detection, READ ERRATA FIRST
;#define USE_BRG16 1 ;xxx uncomment to use 16-bit brg
#define USE_BRBH
;#define USE_TXENABLE 1 ;xxx uncomment to use a tx enable pin
ifdef USE_TXENABLE
#define TXE_DELAY 10 ;xxx time in us to wait before transmitting after pulling the tx enable pin high
#define TRISR_TXE TRISC ;xxx tris register containing tx enable
#define LATR_TXE LATC ;xxx port register containing tx enable
#define TRISB_TXE TRISC6 ;xxx tris bit for tx enable
#define LATB_TXE RC6 ;xxx port bit for tx enable
endif
;------------------------------------------------------------------------------
; Advanced settings
;------------------------------------------------------------------------------
;#define KICK_WD 1 ;xxx uncomment to kick the wd in the rx loop, only enable if the watchdog is enabled
#define PROT_GOTO 1 ;xxx protect goto at 0x00
#define PROT_BL 1 ;xxx protect bootloader
;#define WRITE_VER 1 ;do flash write verification
;#define EWRITE_VER 1 ;do eeprom write verification
ifdef IS_PIC18F
#define BLPLP 9 ;bootloader placement, pages from end
#define BLSIZEP 9 ;bootloader size [pages], used by bootloader protection
endif
ifdef IS_PIC18FJ
#define BLPLP 2 ;bootloader placement, pages from end
#define BLSIZEP 1 ;bootloader size [pages], used by bootloader protection
endif
;------------------------------------------------------------------------------
; Configuration bits, these macros can be found at the end of the inc-files located in
; C:\Program Files\Microchip\MPASM Suite\
;
; These can also be set in MPLAB IDE instead, they are found in Configure->Configuration bits...
;------------------------------------------------------------------------------
; xxx
config FOSC = INTIO67 ;Internal oscillator block, port function on RA6 and RA7
config FCMEN = OFF ;Fail-Safe Clock Monitor disabled
config IESO = OFF ;Oscillator Switchover mode disabled
config PWRT = OFF ;PWRT enabled
config BOREN = OFF ;Brown-out Reset disabled in hardware and software
config BORV = 18 ;VBOR set to 1.90 V nominal
config WDTEN = OFF ;WDT is controlled by SWDTEN bit of the WDTCON register
config WDTPS = 32768 ;Watchdog Timer Postscale Select bits 1:1
config CCP2MX = PORTBE ;CCP2 input/output is multiplexed with RC1
config PBADEN = OFF ;PORTB<4:0> pins are configured as digital I/O on Reset
config LPT1OSC = OFF
config HFOFST = ON
config MCLRE = ON ;MCLR pin enabled RA3 input pin disabled
config STVREN = OFF ;Stack full/underflow will not cause Reset
config LVP = OFF ;Single-Supply ICSP disabled
config XINST = OFF ;Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
config DEBUG = OFF ;Background debugger disabled, RA0 and RA1 configured as general purpose I/O pins
config CP0 = ON ;Block 0 not code-protected
config CP1 = ON ;Block 1 not code-protected
config CPB = ON ;Boot block not code-protected
config CPD = ON ;Data EEPROM not code-protected
config WRT0 = OFF ;Block 0 not write-protected
config WRT1 = OFF ;Block 1 not write-protected
config WRTC = OFF ;Configuration registers not write-protected
config WRTB = OFF ;Boot block not write-protected
config WRTD = OFF ;Data EEPROM not write-protected
config EBTR0 = OFF ;Block 0 not protected from table reads executed in other blocks
config EBTR1 = OFF ;Block 1 not protected from table reads executed in other blocks
config EBTRB = OFF ;Boot block not protected from table reads executed in other blocks
RE: PIC18F46K20 - Mikael Gustavsson - 2014-07-19
Hello,
Please zip and post the modified boot loader project.
Thanks