Hello everyone.
I'm already use ds30 loader for a long time and now I'm trying to compile a new version to test.
Will post what I did until now without success.
I'm using MPLAB X IDE v6.05 with MPLAB XC8 Compiler.
First I opened firmware_18F_XC8 project from source code.
On Project Properties I changed to PIC18F87J60 and chose pic-as. I tried with XC8 but I couldn't go ahead.
On settings.inc
Configured the processor:
I'm using a crystal of 25MHz than changed the configuration for that.
I'm using the UART 1 than I'm using the default configuration.
Changed the configuration bits session for 18F87J60.
Did all configuration, I started to try compile.
The first problem was with STARTADDR.
Following the code I found that STARTADDR is using BLPL64WP.
But this constant is just defined for 18F and not for 18FJ.
Another problem is that, on 18FJ define session, BLPL64WP and BLSIZE64WP are also used.
I tried to solve this errors doing the followed changes.
On IS_18FJ define session:
On ds30loader.s:
Now it´s compiling with success but doesn't work.
The project is attached.
Any help is welcome.
I'm already use ds30 loader for a long time and now I'm trying to compile a new version to test.
Will post what I did until now without success.
I'm using MPLAB X IDE v6.05 with MPLAB XC8 Compiler.
First I opened firmware_18F_XC8 project from source code.
On Project Properties I changed to PIC18F87J60 and chose pic-as. I tried with XC8 but I couldn't go ahead.
On settings.inc
Configured the processor:
Code:
;-------------------------------------------------------------------------------
; Device
;-------------------------------------------------------------------------------
processor 18F87J60 ;xxx
I'm using a crystal of 25MHz than changed the configuration for that.
Code:
;-------------------------------------------------------------------------------
; User preferences
;-------------------------------------------------------------------------------
#define OSCF 25000000 //xxx oscillator frequency (including pll)
#define BLINIT 2000 //xxx hello receive timeout [ms]
#define HELLOTRIES 2 //xxx number of non hello characters received before branching to the user application
#define BLTIME 2000 //xxx data receive timeout [ms]
I'm using the UART 1 than I'm using the default configuration.
Code:
;-------------------------------------------------------------------------------
; UART settings
;-------------------------------------------------------------------------------
#define USE_UART1 1 //xxx uncomment to use uart1
;#define USE_UART2 1 //xxx uncomment to use uart2
#define BAUDRATE 115200 //xxx baudrate
;#define USE_ABAUD 1 //xxx uncomment to use auto baud rate detection, READ ERRATA FIRST
#define USE_BRG16 1 //xxx uncomment to use 16-bit brg
;#define USE_TXENABLE 1 //xxx uncomment to use a tx enable pin
#ifdef USE_TXENABLE
#define TXE_DELAY 10 //xxx time in us to wait before transmitting after pulling the tx enable pin high
#define TRISR_TXE TRISD //xxx tris register containing tx enable
#define LATR_TXE LATD //xxx port register containing tx enable
#define TRISB_TXE TRISD0 //xxx tris bit for tx enable
#define LATB_TXE RD0 //xxx port bit for tx enable
#endif
Changed the configuration bits session for 18F87J60.
Code:
;-------------------------------------------------------------------------------
; Configuration bits, these macros can be found at the end of the inc-files located in
; C:\Program Files\Microchip\MPASM Suite\
;
; These can also be set in MPLAB IDE instead, they are found in Configure->Configuration bits...
;-------------------------------------------------------------------------------
// PIC18F87J60 Configuration Bit Settings
// 'C' source line config statements
// CONFIG1L
config WDT = ON // Watchdog Timer Enable bit (WDT enabled)
config STVR = ON // Stack Overflow/Underflow Reset Enable bit (Reset on stack overflow/underflow enabled)
config XINST = ON // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode enabled)
// CONFIG1H
config CP0 = OFF // Code Protection bit (Program memory is not code-protected)
// CONFIG2L
config FOSC = ECPLL // Oscillator Selection bits (EC oscillator, PLL enabled and under software control, CLKO function on OSC2)
config FOSC2 = ON // Default/Reset System Clock Select bit (Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00)
config FCMEN = ON // Fail-Safe Clock Monitor Enable (Fail-Safe Clock Monitor enabled)
config IESO = ON // Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit (Two-Speed Start-up enabled)
// CONFIG2H
config WDTPS = 32768 // Watchdog Timer Postscaler Select bits (1:32768)
// CONFIG3L
// CONFIG3H
config CCP2MX = ON // ECCP2 MUX bit (ECCP2/P2A is multiplexed with RC1)
config ECCPMX = ON // ECCP MUX bit (ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3)
config ETHLED = ON // Ethernet LED Enable bit (RA0/RA1 are multiplexed with LEDA/LEDB when Ethernet module is enabled and function as I/O when Ethernet is disabled)
Did all configuration, I started to try compile.
The first problem was with STARTADDR.
Following the code I found that STARTADDR is using BLPL64WP.
Code:
#define STARTADDR ( MAX_FLASH - (BLPL64WP * 64 * 2) ) //bootloader placement
But this constant is just defined for 18F and not for 18FJ.
Code:
#ifdef IS_18F
#define BLPL64WP 4 //bootloader placement in 64 word pages from end
#define BLSIZE64WP 4 //bootloader size in 64 word pages, used by bootloader protection
#define BLPLP (BLPL64WP * 64/PAGESIZEW) //bootloader placement, pages from end
#define BLSIZEP (BLSIZE64WP * 64/PAGESIZEW) //bootloader size [pages], used by bootloader protection
#endif
Another problem is that, on 18FJ define session, BLPL64WP and BLSIZE64WP are also used.
Code:
#ifdef IS_18FJ
#define BLPLP512WP 2 //bootloader placement in 512 word pages from end
#define BLSIZE512WP 1 //bootloader size in 512 word pages, used by bootloader protection
#define BLPLP (BLPL64WP * 512/PAGESIZEW) //bootloader placement, pages from end
#define BLSIZEP (BLSIZE64WP * 512/PAGESIZEW)//bootloader size [pages], used by bootloader protection
#endif
I tried to solve this errors doing the followed changes.
On IS_18FJ define session:
Code:
#ifdef IS_18FJ
#define BLPLP512WP 2 //bootloader placement in 512 word pages from end
#define BLSIZE512WP 1 //bootloader size in 512 word pages, used by bootloader protection
#define BLPLP (BLPLP512WP * 512/PAGESIZEW) //bootloader placement, pages from end
#define BLSIZEP (BLSIZE512WP * 512/PAGESIZEW)//bootloader size [pages], used by bootloader protection
#endif
On ds30loader.s:
Code:
#ifdef IS_18FJ
#define STARTADDR ( MAX_FLASH - (BLPLP512WP * 512 * 2) ) //bootloader placement
#else
#define STARTADDR ( MAX_FLASH - (BLPL64WP * 64 * 2) ) //bootloader placement
#endif
Now it´s compiling with success but doesn't work.
The project is attached.
Any help is welcome.