PIC18F45K80 issues [solved]

[doubleeaz]

Really impressed with the bootloader. Downloaded it, modified the settings.inc file, assembled and downloaded to part and worked first time. However, I tried successive attempts to bootload and I get several failures in between successful attempts. The download starts and then the data stops getting sent/received. Then the GUI notes an error in # of data bytes. Just wondering if anyone else has seen this and what was the resolution.

Thanks in advance for any help.



Here is the settings.inc file contents. This is the only file that I changed. The PIC18 hex file that I am bootloading was compiled with the Hitech compiler. Both bootloader and Hitech code were set for release, not debug.


;------------------------------------------------------------------------------
; Device
;------------------------------------------------------------------------------
processor 18F45K80 ;xxx
;------------------------------------------------------------------------------
; Includes
;------------------------------------------------------------------------------
#include "devices.inc"
;------------------------------------------------------------------------------
; User preferences
;------------------------------------------------------------------------------
radix DEC

#define OSCF 16000000 ;xxx oscillator frequency
#define BLINIT 2000 ;xxx hello receive timeout [ms]
#define HELLOTRIES 2 ;xxx number of non hello characters received before branching to the user application
#define BLTIME 2000 ;xxx data receive timeout [ms]

;------------------------------------------------------------------------------
; UART settings
;------------------------------------------------------------------------------
;#define USE_UART1 1 ;xxx uncomment to use uart1
#define USE_UART2 1 ;xxx uncomment to use uart2
#define BAUDRATE 38400 ;xxx baudrate
;#define USE_ABAUD 1 ;xxx uncomment to use auto baud rate detection, READ ERRATA FIRST
;#define USE_BRG16 1 ;xxx uncomment to use 16-bit brg
#define USE_TXENABLE 1 ;xxx uncomment to use a tx enable pin
#ifdef USE_TXENABLE
#define TRISR_TXE TRISD ;xxx tris register containing tx enable
#define LATR_TXE LATD ;xxx port register containing tx enable
#define TRISB_TXE TRISD5 ;xxx tris bit for tx enable
#define LATB_TXE RD5 ;xxx port bit for tx enable
#endif
;------------------------------------------------------------------------------
; Advanced settings
;------------------------------------------------------------------------------
#define PROT_GOTO 1 ;xxx protect goto at 0x00
#define PROT_BL 1 ;xxx protect bootloader

ifdef IS_PIC18F
#define BLPLP 8 ;bootloader placement, pages from end
#define BLSIZEP 8 ;bootloader size [pages], used by bootloader protection
endif

ifdef IS_PIC18FJ
#define BLPLP 2 ;bootloader placement, pages from end
#define BLSIZEP 1 ;bootloader size [pages], used by bootloader protection
endif


;------------------------------------------------------------------------------
; Configuration bits, these macros can be found at the end of the inc-files located in
; C:\Program Files\Microchip\MPASM Suite\
;
; These can also be set in MPLAB IDE instead, they are found in Configure->Configuration bits...
;------------------------------------------------------------------------------

; xxx

CONFIG RETEN = OFF ;Ultra low-power regulator is Disabled (Controlled by REGSLP bit)
CONFIG INTOSCSEL = LOW ;LF-INTOSC in Low-power mode during Sleep
CONFIG SOSCSEL = DIG ;Digital (SCLKI) mode
CONFIG XINST = OFF ;Disabled
CONFIG FOSC = HS1 ;HS oscillator (Medium power, 4 MHz - 16 MHz)
CONFIG PLLCFG = OFF ;Disabled
CONFIG FCMEN = OFF ;Disabled
CONFIG IESO = OFF ;Disabled
CONFIG PWRTEN = ON ;Enabled
CONFIG BOREN = OFF ;Disabled in hardware, SBOREN disabled
CONFIG BORV = 0 ;3.0V
CONFIG BORPWR = MEDIUM ;BORMV set to medium power level
CONFIG WDTEN = OFF ;WDT disabled in hardware; SWDTEN bit disabled
CONFIG WDTPS = 1048576 ;1:1048576
CONFIG MCLRE = ON ;MCLR Enabled, RG5 Disabled
CONFIG STVREN = ON ;Enabled
CONFIG BBSIZ = BB1K ;1K word Boot Block size
CONFIG CP0 = OFF ;Disabled
CONFIG CP1 = OFF ;Disabled
CONFIG CP2 = OFF ;Disabled
CONFIG CP3 = OFF ;Disabled
CONFIG CPB = OFF ;Disabled
CONFIG CPD = OFF ;Disabled
CONFIG WRT0 = OFF ;Disabled
CONFIG WRT1 = OFF ;Disabled
CONFIG WRT2 = OFF ;Disabled
CONFIG WRT3 = OFF ;Disabled
CONFIG WRTC = OFF ;Disabled
CONFIG WRTB = OFF ;Disabled
CONFIG WRTD = OFF ;Disabled
CONFIG EBTR0 = OFF ;Disabled
CONFIG EBTR1 = OFF ;Disabled
CONFIG EBTR2 = OFF ;Disabled
CONFIG EBTR3 = OFF ;Disabled
CONFIG EBTRB = OFF ;Disabled

;------------------------------------------------------------------------------
; End of file
;------------------------------------------------------------------------------