2012-11-10, 00:23:35
Hi Mikael:
Awesome -- I love this bootloader. I enabled debug for my 18F27J13 code and during parse now see (near the end):
Bootloader start address: 0x1F800
Bootloader end address: 0x1FBFF
I had previously found the start address of 0x1F800 in the intel hex file (after deciphering the "extended" start address record). The problem I was still having was when I did a memory reservation ORG of:
#org 0x1F800, 0x1FFFF {}
I was getting an error. A call to CCS later, and I found that I NEEDED TO CHANGE THIS TO:
#org 0x1F800, 0x1FFF7 {}
since the last eight bytes are now config words on this micro. Duh.
But why is the loader so far down in flash when it only needs to avoid the 8 top bytes? Seems like it could start at 0x1F900 with no problem, as the other versions only take 700-or-so-bytes. But I'm not complaining, since it is unlikely I will hit anything near the 126K ceiling with the 18F27J13.
I also see that the debug output says "Flash page 0 is used, 0x00 - 0x3FF" so I guess that answers my original question about how large a page is. Is that 1K-per-page a microchip definition or a dsLoader definition?
Many thanks for making this bootloader available to everyone. It is the first time a programmer has been able to target pretty-much any pic, and not be at the mercy of whatever few supported micros were available for a gratis bootloader. For years I used an 18F876 loader, and then when I needed more rom found an 18F252 loader, and then an 18F2620 loader. But these all forced me to conform to the pics available and the clock speeds that were hard-coded in their bootloaders. Even though there was a learning curve with MPLAB with dsLoader, it is so nice to be able to not only target a specific chip, but also be able to set up any clock configuration, AND be able to add a bit of user code to handle chip errata situations. Thanks again.
Awesome -- I love this bootloader. I enabled debug for my 18F27J13 code and during parse now see (near the end):
Bootloader start address: 0x1F800
Bootloader end address: 0x1FBFF
I had previously found the start address of 0x1F800 in the intel hex file (after deciphering the "extended" start address record). The problem I was still having was when I did a memory reservation ORG of:
#org 0x1F800, 0x1FFFF {}
I was getting an error. A call to CCS later, and I found that I NEEDED TO CHANGE THIS TO:
#org 0x1F800, 0x1FFF7 {}
since the last eight bytes are now config words on this micro. Duh.
But why is the loader so far down in flash when it only needs to avoid the 8 top bytes? Seems like it could start at 0x1F900 with no problem, as the other versions only take 700-or-so-bytes. But I'm not complaining, since it is unlikely I will hit anything near the 126K ceiling with the 18F27J13.
I also see that the debug output says "Flash page 0 is used, 0x00 - 0x3FF" so I guess that answers my original question about how large a page is. Is that 1K-per-page a microchip definition or a dsLoader definition?
Many thanks for making this bootloader available to everyone. It is the first time a programmer has been able to target pretty-much any pic, and not be at the mercy of whatever few supported micros were available for a gratis bootloader. For years I used an 18F876 loader, and then when I needed more rom found an 18F252 loader, and then an 18F2620 loader. But these all forced me to conform to the pics available and the clock speeds that were hard-coded in their bootloaders. Even though there was a learning curve with MPLAB with dsLoader, it is so nice to be able to not only target a specific chip, but also be able to set up any clock configuration, AND be able to add a bit of user code to handle chip errata situations. Thanks again.