2012-12-06, 23:38:45
You should probably review the configuration bits. It appears the PLL is enabled. The FCY equ is correct for a 8MHz crystall without PLL.
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24FJ256DA210 help
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24FJ256DA210 help - by rturnpaugh - 2012-11-30, 21:10:14
RE: 24FJ256DA210 help - by Mikael Gustavsson - 2012-12-05, 23:09:34
RE: 24FJ256DA210 help - by rturnpaugh - 2012-12-06, 17:03:24
RE: 24FJ256DA210 help - by Mikael Gustavsson - 2012-12-06, 23:38:45
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