2014-01-30, 01:07:43
Hello,
I have try to using the ds30loader on a PIC18F26K20, but it seems not work.
Clicking on Check for bl I obtain:
I'm sure that:
- The UART work on the board
- I have changed the config as reported later
- No external oscillator are present on the board
- I have changed project device with PIC18F26K20
- I have changed line in settings.inc
processor 18F26K20 ;xxx
- I have commented error on ADCON1 (no analog with this pins)
;error Do you need to co....
There are some other thing to do?
Thank you in advance
;;;;;; CONFIG :;;;;;;;;;;;;;;;
; CONFIG1H
CONFIG FOSC = INTIO67 ; Oscillator Selection bits (External RC oscillator, port function on RA6)
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
CONFIG IESO = OFF ; Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
; CONFIG2L
CONFIG PWRT = OFF ; Power-up Timer Enable bit (PWRT disabled)
CONFIG BOREN = SBORDIS ; Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
CONFIG BORV = 18 ; Brown Out Reset Voltage bits (VBOR set to 1.8 V nominal)
; CONFIG2H
CONFIG WDTEN = ON ; Watchdog Timer Enable bit (WDT is always enabled. SWDTEN bit has no effect)
CONFIG WDTPS = 32768 ; Watchdog Timer Postscale Select bits (1:32768)
; CONFIG3H
CONFIG CCP2MX = PORTC ; CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
CONFIG PBADEN = ON ; PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset)
CONFIG LPT1OSC = OFF ; Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
CONFIG HFOFST = OFF ; HFINTOSC Fast Start-up (HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.)
CONFIG MCLRE = ON ; MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
; CONFIG4L
CONFIG STVREN = ON ; Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
CONFIG LVP = OFF ; Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
CONFIG XINST = OFF ; Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
; CONFIG5L
CONFIG CP0 = OFF ; Code Protection Block 0 (Block 0 (000800-003FFFh) not code-protected)
CONFIG CP1 = OFF ; Code Protection Block 1 (Block 1 (004000-007FFFh) not code-protected)
CONFIG CP2 = OFF ; Code Protection Block 2 (Block 2 (008000-00BFFFh) not code-protected)
CONFIG CP3 = OFF ; Code Protection Block 3 (Block 3 (00C000-00FFFFh) not code-protected)
; CONFIG5H
CONFIG CPB = OFF ; Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
CONFIG CPD = OFF ; Data EEPROM Code Protection bit (Data EEPROM not code-protected)
; CONFIG6L
CONFIG WRT0 = OFF ; Write Protection Block 0 (Block 0 (000800-003FFFh) not write-protected)
CONFIG WRT1 = OFF ; Write Protection Block 1 (Block 1 (004000-007FFFh) not write-protected)
CONFIG WRT2 = OFF ; Write Protection Block 2 (Block 2 (008000-00BFFFh) not write-protected)
CONFIG WRT3 = OFF ; Write Protection Block 3 (Block 3 (00C000h-00FFFFh) not write-protected)
; CONFIG6H
CONFIG WRTC = OFF ; Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
CONFIG WRTB = OFF ; Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
CONFIG WRTD = OFF ; Data EEPROM Write Protection bit (Data EEPROM not write-protected)
; CONFIG7L
CONFIG EBTR0 = OFF ; Table Read Protection Block 0 (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
CONFIG EBTR1 = OFF ; Table Read Protection Block 1 (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
CONFIG EBTR2 = OFF ; Table Read Protection Block 2 (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
CONFIG EBTR3 = OFF ; Table Read Protection Block 3 (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)
; CONFIG7H
CONFIG EBTRB = OFF ; Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
I have try to using the ds30loader on a PIC18F26K20, but it seems not work.
Clicking on Check for bl I obtain:
Quote:Searching for bl . response timed out
Found PIC24FJ256DA110
Firmware version timed out
I'm sure that:
- The UART work on the board
- I have changed the config as reported later
- No external oscillator are present on the board
- I have changed project device with PIC18F26K20
- I have changed line in settings.inc
processor 18F26K20 ;xxx
- I have commented error on ADCON1 (no analog with this pins)
;error Do you need to co....
There are some other thing to do?
Thank you in advance
;;;;;; CONFIG :;;;;;;;;;;;;;;;
; CONFIG1H
CONFIG FOSC = INTIO67 ; Oscillator Selection bits (External RC oscillator, port function on RA6)
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
CONFIG IESO = OFF ; Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
; CONFIG2L
CONFIG PWRT = OFF ; Power-up Timer Enable bit (PWRT disabled)
CONFIG BOREN = SBORDIS ; Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
CONFIG BORV = 18 ; Brown Out Reset Voltage bits (VBOR set to 1.8 V nominal)
; CONFIG2H
CONFIG WDTEN = ON ; Watchdog Timer Enable bit (WDT is always enabled. SWDTEN bit has no effect)
CONFIG WDTPS = 32768 ; Watchdog Timer Postscale Select bits (1:32768)
; CONFIG3H
CONFIG CCP2MX = PORTC ; CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
CONFIG PBADEN = ON ; PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset)
CONFIG LPT1OSC = OFF ; Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
CONFIG HFOFST = OFF ; HFINTOSC Fast Start-up (HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.)
CONFIG MCLRE = ON ; MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
; CONFIG4L
CONFIG STVREN = ON ; Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
CONFIG LVP = OFF ; Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
CONFIG XINST = OFF ; Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
; CONFIG5L
CONFIG CP0 = OFF ; Code Protection Block 0 (Block 0 (000800-003FFFh) not code-protected)
CONFIG CP1 = OFF ; Code Protection Block 1 (Block 1 (004000-007FFFh) not code-protected)
CONFIG CP2 = OFF ; Code Protection Block 2 (Block 2 (008000-00BFFFh) not code-protected)
CONFIG CP3 = OFF ; Code Protection Block 3 (Block 3 (00C000-00FFFFh) not code-protected)
; CONFIG5H
CONFIG CPB = OFF ; Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
CONFIG CPD = OFF ; Data EEPROM Code Protection bit (Data EEPROM not code-protected)
; CONFIG6L
CONFIG WRT0 = OFF ; Write Protection Block 0 (Block 0 (000800-003FFFh) not write-protected)
CONFIG WRT1 = OFF ; Write Protection Block 1 (Block 1 (004000-007FFFh) not write-protected)
CONFIG WRT2 = OFF ; Write Protection Block 2 (Block 2 (008000-00BFFFh) not write-protected)
CONFIG WRT3 = OFF ; Write Protection Block 3 (Block 3 (00C000h-00FFFFh) not write-protected)
; CONFIG6H
CONFIG WRTC = OFF ; Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
CONFIG WRTB = OFF ; Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
CONFIG WRTD = OFF ; Data EEPROM Write Protection bit (Data EEPROM not write-protected)
; CONFIG7L
CONFIG EBTR0 = OFF ; Table Read Protection Block 0 (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
CONFIG EBTR1 = OFF ; Table Read Protection Block 1 (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
CONFIG EBTR2 = OFF ; Table Read Protection Block 2 (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
CONFIG EBTR3 = OFF ; Table Read Protection Block 3 (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)
; CONFIG7H
CONFIG EBTRB = OFF ; Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
